This invention relates generally to the testing of integrated semiconductor logic circuits including large scale integrated (LSI) circuits and very large scale integrated (VLSI) circuits (hereinafter referred to collectively as LSI circuits) using logic scan design (LSD) techniques and in particular to providing programmable fault insertion logic within the LSI circuit, and modules and systems comprising the LSI circuits, for verifying fault detection capability.
With the advent of large scale integration improved methods of testing LSI circuits have been deviced to accomplish a reliable level of testing to measure the performance of a functional integrated circuit (IC) chip or a plurality of said chips in a module under test. Prior to the existence of LSI the AC parameters of circuits on an integrated circuit chip were measured such as the rise time, fall time, individual circuit delay, etc., in addition to performing DC measurements. The packaging of an LSI chip can accommodate only a limited number of input-output pins thereby limiting the amount of parametric and functional testing that can be performed on an LSI device comprising large quantities of conventional logic design.
One of the known test methods for testing LSI devices and systems employing LSI devices is Level Sensitive Scan Design (LSSD) which is described in U.S. Pat. Nos. 3,761,695, 3,783,254, 7,784,907 and in the publication "A Logic Design Structure for LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-468. In a system employing LSSD, a logic system is defined as being "level sensitive" if, and only if, the steady state response to any allowed input state change is independent of the circuit and wire delays within the system. Also, if an input stage change involves the changing of more than one input signal, then the response must be independent of the order in which they change. A level sensitive system is assumed to operate as a result of a sequence of allowed input changes with sufficient time lapse between changes to allow the system to stabilize in the new internal state. To implement a level sensitive system, the logic organization is such that all internal storage elements function as shift register latches or portions of shift register latchs having access and controls independent of the system access and controls thereby transforming sequential circuits into combinational circuits. Thus, LSSD testing is performed by shifting test data via a scan-in input into a serial chain of logic on an LSI device having storage elements implemented with shift register latches, applying test vectors to the primary inputs of the device under test, and shifting the data out via a scan-out output to compare it to known good test data.
In addition to the testing of LSI devices via an LSD or LSSD technique that arranges for all internal logic states to be held in registers that can be serially accessed allowing the internal states to be observed and controlled, it is also important to be able to verify and demonstrate that a testing method being used does indeed detect a failure condition in an LSI circuit in the manner expected. Such testing and verification are also required for the next two levels of integration wherein a plurality of LSI circuits are mounted on a module card and a plurality of module cards are assembled into a system.